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CAD Lab - SPICE circuit simulation: LTSpice lab exploration: Use LTSpice to explore the simulation of simple circuits. You can get LTSpice here. If you have trouble downloading it from Linear Technology please download (not the latest version) here for Mac OSX and Windows. Start with the simple circuit that demonstrates the abstraction of a transistor into a composite circuit that includes a switch, a linear resistor and a capacitor for the inverter (LTSpice file) and create a circuit that abstracts the behavior of NAND gate in CMOS. Simulate the circuit, experiment with changing the width and lengths of MOS transistors and corresponding values for Ron for PMOS and NMOS devices. Due: March 2
The conversion of the schematic diagram into a VERILOG description is usefull for compiling the schematic diagram into layout using Microwind. The verilog description is a text with a predefined syntax. Basically, the text includes a description of the module (name, input, output), the internal wires, and the list of primitives. An example of veriolog file generated by DSCH is given below. 2b1af7f3a8